1. Field of the Invention
This invention relates to an overflow detection circuit and, more particularly, to a circuit detecting an overflow in a shifter which is adapted for shifting bits of input data.
2. Description of the Background Art
In a data arithmetic portion in a microprocessor or a single processor, a shifter is usually provided for shifting bits of input data, in the form of binary codes by moving the digit to which the bits belong.
When the shifter shifts the input data in this manner, errors may be caused in the produced output data. For example, when the input data is "00001010" in two's complement representation (10 in decimal representation) and is shifted toward the left by four bits, the output data turns out to be "10100000" (-96 in decimal representation), which is not correct. The two's complement representation is the method of representing data in which, when the data is negative, the logical states of all the bits are inverted and unity is added to the least significant bit. The most significant bit or MSB is used as the sign bit for indicating the sign, that is the plus or minus of the data. Thus the data is positive or negative when the MSB is 0 or 1, respectively. In the above example, when the original input data "00001010" is shifted towards left by 4 bits, the output data turns out to be "1010000". Thus the fourth bit "1" from the right of the input data is moved after shifting to the position of the most significant bit (MSB) so that the bit data which inherently indicate the figure or numeral now indicates the sign. As a result, an error is produced in the output data. Thus an excess shifting of the input data causes an overflow to produce an error in the output data. This is referred to as an overflow in the shifter.
Therefore, before shifting the input data by the shifter, it is necessary to check if an overflow is caused in the shifter as a result of shifting and to discontinue the shifting operation to prevent the error from being produced in the output data, when it is found that the overflow is caused by the shifter. FIG. 1 is a schematic block diagram showing the arrangement of the overflow detection circuit in the conventional shifter. In this figure, 8-bit data I7 to I0 to be shifted, are entered into a coincidence circuit 31. This coincidence circuit 31 compares the data of the most significant bit and the other bits of the input data and outputs "0" or "1" when the two bits are coincident or not coincident with each other, respectively. Such comparison in the coincidence detection circuit 31 is performed for each of the 7 bits. An inversion of the most significant bit data is added to the least significant bit or LSB of the 7-bit comparison result signal. Thus, when the data entered for shifting is "00001010", for example, the output of the coincident detection circuit 31 proves to be "00010101". This 8-bit signal is entered to a priority rank detector 32.
A priority rank detector 32 is a circuit which sets the bit with the highest priority rank, that is the upper order side bit with the data "1", to "1" and the remaining bits to "0". Thus, when the data entered into the priority rank detector 32 is "00010101", for example, the output of the priority rank detector 32 proves to be "00010000". The output of the priority rank detector 32 is entered into a magnitude comparator 33.
The magnitude comparator 33 decides which of the output signal from the priority rank detector 32 or shift select signals S7 to S0 is larger. The shift select signals S7 to S0 are signals indicating the amount of shift, that is, the number of bits by which the input data is to be moved. A switch select signal in a shift array, for example, is used as the shift select signal. Assuming that the input data is to be shifted toward left by two bits, the shift select signals S7 to S0 prove to be "00100000", for example. When the output of the priority rank detector 32 is larger than the shift select signals S7 to S0, the magnitude comparator 33 decides that an overflow has been caused, and outputs "1". When the output of the priority rank detector 32 is lesser than or equal to the shift select signal, the magnitude comparator 33 decides that an overflow has not been caused, and outputs "0". In the above example, the magnitude comparator 33 decides that an overflow has not been caused and outputs "0" when the amount of leftword shift is 0, 1, 2 or 3, and decides that an overflow has been caused and outputs "1" when the amount of leftword shift is 4, 5, 6 or 7.
FIG. 2 is a logical circuit diagram showing an arrangement of the priority rank detector 32 shown in FIG. 1. In this figure, the priority rank detector 32 is made up of a plurality of OR gates 326 to 320, and a plurality of exclusive OR gates 326' to 320'. When output data X7 to X0 are entered to the priority rank detector 32 from the coincidence detection circuit 31, data comparison is made in the priority rank detector 32 on the bit-by bit basis from the most significant bit. Only the upper order side bit on which "1" appears first becomes non-coincident so that "1" is outputted from the associated exclusive 0R gate. Outputs from the remaining exclusive OR gates are "0" since two inputs are coincident in these exclusive 0R gates.
With the above described conventional overflow detection circuit, problems are raised that the circuit is formed by a large number of elements and the detection time is protracted. The coincidence detection circuit 31, for example, is made up of a plurality of exclusive 0R gates provided for each bit. The priority rank detector 32 is made up of a plurality of OR gates 326 to 320 and a plurality of exclusive OR gates 326' to 320', as shown in FIG. 2. The magnitude detector 33 includes subtractors formed by full adders, each associated with one bit. The exclusive OR gates are in need of a larger number of transistors than in the case of the basic gating circuits such an AND or OR gates. On the other hand, each full adder is in need of at least 24 transistors. Thus the conventional overflow detection circuit shown in FIG. 1 is in need of an extremely large number of transistors since it is formed by a large number of exclusive OR gates and full adders, so that the size and cost of the circuit are increased. Inasmuch as the coincident detection circuit 31 and the priority rank detector 32 are arranged so that signals are propagated bit by bit from the most significant bit to the least significant bit, a delay in signal propagation is caused in dependence upon the number of bits of the processed data. In the magnitude comparator 33, a delay is similarly caused due to chain of carries in the full adders. With the overflow detection circuit shown in FIG. 1, the coincidence detection circuit 31, the priority rank detector 32 and the magnitude comparator 33 are connected in series and hence the delay times in the circuits 31 to 33 are summed together so that the signal propagation time since the application of the input data to the ultimate overflow detection is prolonged resulting in retarded detection. In general, in a microprocessor employing a shifter, the circuit as a whole is driven in synchronism with clocks, so that the delay time of the worst delay route, that is the route having the longest delay time, determines the operating speed performance of the overall circuit. Thus the probability is high that the overflow detection circuit of FIG. 1 proves to be the worst delay route. Hence, there is a risk that the overflow detection circuit of FIG. 1 deteriorates the processing performance of the entire circuit.